| Processor |
Intel® Pentium® M processor
at speeds of 1.6GHz to 1.8GHz* *Higher speeds as available |
| Form Factor |
The OSS-CPU-600-M is a single-slot module
(4HP width) with a 6U height and is fully compliant with
the CompactPCI® Core |
| Specification |
PICMG® 2.0, R3.0. |
| Chipset |
The OSS-CPU-600-M uses Intel’s E7501
chipset which provides support for DDR200/266 memory with
ECC and a high-speed Hub Link 2.0 interface. Intel® Pentium® M
processors support a 400MHz FSB CompactPCI® BUS. The
OSS-CPU-600-M provides direct support for up to seven expansion
CompactPCI slots at 32-bit/33MHz and up to four expansion
slots at 64-bit/66MHz. Each slot provides support for PCI
Bus mastering. The CompactPCI bus can be turned off via the
OSS-CPU-600-M’s CompactPCI bus switches for server
blade applications. |
| PMC Option Card Slot |
PMC 32/64-bit, 33/66MHz option cards are supported
by the OSS-CPU-600-M via an access slot in the SBC’s
front panel. |
| Bus Speed |
CompactPCI® Bus: 32-bit/33MHz, 32-bit/66MHz,
64-bit/33MHz, 64-bit/66MHz |
| |
PCI-X Local Bus: 64-bit/100MHz |
| |
PCI Local Bus: 32-bit/33Mhz & 64-bit/100MHz |
| |
Hub Link 2.0*: 1GB/s |
| |
System/FSB: 400MHz |
| |
* Hub Link D is routed to J4 for high-speed
interface usage on the optional Rear Transition Module, OSS-CPU-600S/P-M-RTM |
| Packet Switching Backplane Support |
Channel B of each Ethernet controller provides
a redundant 10/100/1000Base-T Ethernet interface via connector
J3 to the CompactPCI backplane. This allows Ethernet communication
and control between the OSS-CPU-600-M and other boards in
the CompactPCI chassis. The interface implementation is fully
compatible with the PICMG® 2.16, R1.0 specification |
| IPMI & Hot Swap Support |
The OSS-CPU-600-M supports the Intelligent
Platform Management Interface (IPMI, PICMG® 2.9, R1.0),
Hot Swap (PICMG® 2.1, R2.0) and Hot Swap Infrastructure
(PICMG® 2.12, R2.0) specifications. |
| Local Storage Option |
A Compact Media Daughter Card (CMDC) plugs
into connector P11A on the OSS-CPU-600-M and provides support
for either a CompactFlash™ or Microdrive® storage
device. In server blade applications this option is useful
for storing the operating system and application. |
| BIOS (Flash) |
The OSS-CPU-600-M’s BIOS is AMIIOS8® with
IPMI extensions. The flash BIOS resides in the 82802 Firmware
Hub (FWH). |Some of the key features of the BIOS are: |
| |
·Boot from network, USB mass storage
devices, IDE, ATAPI or SCSI |
| |
·Serial port console redirection to
support headless operation |
| |
·IPMI v1.5 Baseboard Management Controller
(BMC) support |
| |
·BMC console (text) redirection |
| |
·Intel SpeedStep® support |
| |
·Optional CompactPCI bus support |
| |
·Supports either system board or blade
card applications |
| Cache Memory (L2) |
Intel® Pentium® M processors 1.8GHz
and above have a 2MB on-die, Level 2 (L2) cache memory with
Advanced Transfer Cache architecture. Processors below 1.8GHz
have a L2 cache of 1MB. The processors also have a Level
1 (L1) 32K instruction and data cache. |
| DDR200/266 Memory |
The OSS-CPU-600-M provides a single channel
DDR memory interface terminating at a DIMM socket. The memory
interface supports up to 2GB of memory and has an interface
bandwidth of 1600MB/s. The SBC accepts a single ECC, registered
PC1600 or PC2100 DIMM. |
| PCI-X and PCI Local Bus Interfaces |
The OSS-CPU-600-M’s on-board PCI-X bus,
which runs at 64-bit/100MHz, supports the SBC’s dual
Ethernet controllers to provide full-speed Gigabit functionality
to the module’s LAN ports and backplane connector J3. |
| Primary PCI Interface |
The Primary PCI interface runs at 32-bit/33MHz
and supports the on-board video interface. |
| Secondary PCI Interfaces |
Two secondary PCI interfaces are 32/64-bit,
operating at 33/66MHz and drive the local PMC slot and CompactPCI
passive backplanes. The OSS-CPU-600-M features CompactPCI
bus switches for turning off the bus in applications not
requiring CompactPCI bus support. |
| Standards |
·PCI Local Bus Specification 2.1 |
| |
·PCI-SIG, PCI-X Addendum to the PCI
Local Bus Specification, Revision 1.0b |
| |
·CompactPCI® Core Specification,
PICMG® 2.0, R3.0 |
| |
·CompactPCI® Hot Swap Specification,
PICMG® 2.1, R2.0 |
| |
·CompactPCI® Hot Swap Infrastructure
Specification, PICMG® 2.12, R2.0 |
| |
·CompactPCI® PCI Mezzanine Card
(PMC) I/O Pin Assignment Specification, PICMG® 2.3, R1.0 |
| |
·CompactPCI® System Management
Specification, PICMG® 2.9, R1.0 (Intelligent Platform
Management Interface (IPMI) support) |
| |
·CompactPCI® PCI Telecom Mezzanine
Card (PTMC) Specification, PICMG® 2.15, R1.0 CompactPCI® Packet
Switching Backplane Specification, PICMG® 2.16, R1.0 |
| Dual Ethernet Interfaces |
10/100/1000BASE-T:|An internal 64-bit/100MHz
PCI-X bus connects to the CP16’s Ethernet controllers,
ensuring full-speed Gigabit Ethernet in applications using
1000Base-T Ethernet communications. Channel A on each controller
supports 10/100/1000Base-T Ethernet connectivity to the RJ-45
connectors located on the CP16’s front panel. Channel
B on each controller enables the SBC’s Packet Switching
Backplane capability. |
| Rear Transition Module (optional) |
The RTM25 is available for use in CP16 applications
where rear access I/O panel connectors are required. The
RTM25 is not required for the CP16 to function. The RTM25’s
optional Ultra320 SCSI interfaces utilize the high-speed,
1GB/s Hub Link 2.0 interface from the CP16’s E7501
Memory Controller Hub. |
| Universal Serial Bus (USB) |
A total of four (4) USB ports are available
on the CP16. USB ports 0 and 1 are located on the CP16’s
front panel and USB ports 2 and 3 are available at connector
J5. The CP16’s E7501 chipset supports USB revision
1.1. |
| Eide Ultra ATA/100 Interfaces (dual) |
Dual high-performance PCI EIDE interfaces
are capable of supporting up to two IDE disk drives each
in a master/slave configuration. The interfaces support Ultra
ATA/100 with synchronous ATA mode transfers up to 100MB per
second. The interfaces are routed through backplane connector
J5. Dual EIDE connectors are available on the optional RTM25
rear transition module. |
| Ultra XGA Video Interface |
The ATI® M6-C16H video controller enables
2D/3D video acceleration and provides 16MB of integrated
video DDR memory. The video controller supports pixel resolutions
up to 1600 x 1200 (UXGA). Software drivers are available
for most popular operating systems. |
| Serial Interface |
The Super I/O controller supports two full-function
serial ports with independently programmable baud rates.
The controller has two high-speed, NS16C550 compatible, UARTs
with Send/Receive 16-Byte FIFOs. The IRQ for each serial
port has BIOS selectable addressing. Serial port 1 is located
on the CP16’s front panel and serial port 2 is routed
to the RTM25 via backplane connector J5. Serial devices may
be attached to the front panel and to the RTM25. |
| Floppy Drive Interface |
The CP16 supports up to two floppy disk drives.
Drives can be 360K to 2.88MB, in any combination. The floppy
drive interface is routed to the RTM25 via backplane connector
J5. |
| Keyboard and PS/2 Mouse Interfaces |
The keyboard and mouse interfaces are routed
to the RTM25 via backplane connector J5. A mini DIN connector
located on the RTM25 provides an external interface for a
PS/2 mouse and keyboard. A "Y" adapter plugged
into the mini DIN connector allows the PS/2 mouse and keyboard
to share the same port. Internal PS/2 mouse and keyboard
headers are also available on the RTM25. A self-resetting
fuse on the RTM25 protects the +5V line of the keyboard and
the mouse. |
| Power Requirements |
Typical Values |
| |
CPU +5V* +3.3V* |
| |
1.8GHz t.bdA t.bdA |
| |
1.6GHz t.bdA t.bdA |
| |
+12V @ tbdmA |
| |
-12V @ <100mA |
| Battery |
Built-in lithium battery for data retention
of CMOS memory. |
| Temperature/Environment |
Operating Temperature 0° to 55° C. |
| |
Storage Temperature: -20° to 70° C. |
| |
Humidity: 5% to 90% non-condensing |
| |
Cooling Solution: Passive Heat Sink |
| Agency Approvals & Industry Compliance |
·Designed for UL 1950, CAN/CSA C22.22
Number 950-95, EN55022:1994/A2:1997, CLASS A, EN55024, EN6100-6-2:1999,
EN61000-3-2:2001 |
| |
·The CP16 is designed for NEBS/ETSI
compliance. |
| Mean Time Between Failures (MTBF) |
BD POH (Power-On Hours) at 40 °C., per
Bellcore |
